Highly integrated semiconductor circuits are increasingly important, particularly in producing battery-operated devices such as cell phones, portable computers (such as laptops), notebook computers and PDAs, wireless email terminals, MP3 audio and video players, portable wireless web browsers and the like, and these sophisticated integrated circuits increasingly include on-board data storage.
As is known in the art, such data storage may take the form of dynamic memory cells in which arrays of capacitive storage memory cells are provided, each memory cell having an access transistor. Data stored in such memory cells is actually a charge stored on a small capacitor, and the data is typically accessed by outputting the stored charge to a bit line coupled to a sense amplifier. The data is output when the access transistor is activated, typically by a word line coupled to the gate or control terminal of the transistor. Sense amplifiers are differential amplifiers. The input and output lines coupled from the memory cells to the memory array sense amplifier are typically referred to as bit lines or column lines. The sense amplifier operates by receiving a small differential voltage on one of the bit lines, while the other bit line remains at, or is coupled to, a reference voltage. To enable large arrays of memory cells to be used in implementing a memory device, pairs of global bit lines coupled to one or more differential sense amplifiers are often routed though the memory array, while pairs of local bit lines for transmitting and receiving read and write data to and from the sense amplifiers are formed in columns in sub-arrays. The local bit lines are usually arranged as columns coupled to rows of memory cells. The global bit lines may also be coupled to another differential sense amplifier, and finally to an input/output circuit that transfers the memory array data to and from other devices.
Dynamic memory cells may be used in stand alone or commodity memory devices such as DRAM integrated circuits (ICs). These ICs are usually supplied in the form of cards populated with several commodity DRAM ICs to make a complete array of memory, for example, so called SIMM or DIMM cards. These cards are then provided as a finished memory for a desktop or laptop computer. Increasingly, embedded dynamic memory is becoming important in the production of advanced integrated circuits. These embedded memory modules may be a portion of an integrated circuit that provides an entire system in one IC, so-called system on a chip (SOC) or system on integrated circuit (SOIC) devices. These SOC devices may provide, for example, all of the circuitry needed to implement a cell phone, personal data assistant (PDA), digital VCR, digital camcorder, digital camera, MP3 player, or the like in a single integrated circuit. The embedded memory arrays used in such devices must be very space efficient, power efficient, reliable and compatible with semiconductor processes that form logic circuitry and other types of circuitry on-board the same integrated device. Typically, the embedded dynamic memory in such integrated circuits is referred to as e-DRAM.
FIG. 1 depicts a small portion of a typical dynamic memory circuit. Dynamic memory must be refreshed periodically because the stored charge in the cells leaks away over time. As is known in the art, timing circuitry (hardware or software) will track the time elapsed since the last access to the memory cells and will cause the circuit to “refresh” the cells when needed. Refresh is done simply by performing a read followed by a restore or “write back” cycle to the cells.
Any read of a memory cell such as the memory cell MC in FIG. 1 is destructive, so the cell is always restored or rewritten at the end of the cycle. A “write” is simply a read cycle with write data impressed on the respective local bit line during the “restore” portion of the cycle. For a write, the read data is replaced or overwritten with the write data and then written into the cell. Thousands or even millions of these memory cells are used to form a practical dynamic memory device.
In FIG. 1, memory cell MC is coupled at an intersection between a row or word line WL and a column or bit line BL. Although only one memory cell MC is depicted, another cell will be placed at the intersection of each of a plurality of word lines WL and the bit line BL. Similarly, a plurality of memory cells will also be placed at the intersections of each of a plurality of row lines WL (only one of which is depicted in FIG. 1) and the complementary bit line ZBL of FIG. 1. A portion of a memory circuit may have 8, 16, 32, 64, 128 or more columns, typically arranged in word widths, and many word lines or rows typically arranged across the bit lines. Conventionally, the word lines or rows are laid out orthogonally to the columns as depicted in the simplified schematic of FIG. 1, although other arrangements are also known. Sense amplifier SA is coupled to a pair of local bit lines BL. Each pair of local bit lines BL and ZBL in the array will be coupled to such a sense amplifier SA. The bit lines BL and ZBL are each further coupled to the global bit lines GBL and ZGBL through the use of column select control line SSL and column select coupling transistors T28 and T29. In this manner many, many columns of memory cells may be arranged in sub-arrays and selectively coupled to the global bit lines; for a particular memory cycle, one memory cell, such as memory cell MC, is coupled to each pair of the global bit lines. The global bit lines GBL and ZGBL are again coupled to another differential sense amplifier (not shown) and the amplified sensed data is then output to I/O lines. The I/O lines will be arranged in a group to form a word of data for each cycle, for example, the memory device may be an X8 device with eight I/O lines forming a word, and X16, X32, X64 and X128 wide devices are also known.
The timing of a memory cycle for the prior art is depicted in FIG. 2. Prior to the timing as shown in FIG. 2, the BLEQ signal of FIG. 1 is active and forces the local bit lines BL and ZBL to a common, equalized voltage or “pre-charged” potential Vref, “precharged” using transistors T10, T24, and T25. In DRAM devices known in the prior art the precharge voltage Vref is typically set at a voltage approximately one half of the positive supply voltage Vdd.
The memory access cycle begins when the active word line WL transitions to a row select state. Since the memory access transistor Tc in this example circuit of FIG. 1 is an N-channel MOS transistor, the word line WL transitions to a high positive voltage to cause the transistor Tc to couple the capacitor Cc to the bit line BL. The word line WL is supplied by an address decode circuit (not depicted) that determines which row in the memory array is active based on an address previously supplied to the memory array. This address decode circuitry is well known in the prior art and is not further described here. A short time after the word line WL goes active by transitioning to a positive voltage level, the access transistor Tc couples the capacitor Cc of the example memory cell MC to the respective bit line BL, and the “charge sharing” portion of the cycle begins. If the stored data in memory cell MC is a logical “1” the storage capacitor Cc will add voltage to the bit line equalization voltage, already on BL during the charge sharing operation. In response, a small voltage increase ΔVBL will be seen on the bit line BL, as shown in FIG. 2. If the stored data is a logical “0” the storage capacitor Cc may subtract voltage from the bit line, for example, by charging the capacitor Cc in the memory cell from the bit line BL. These logical data assignments are arbitrary and may be reversed, as is well known in the art.
Shortly after the “charge sharing” has begun, the timing diagram of FIG. 2 further illustrates the sensing portion of the memory cycle. In this part of the memory cycle, the control line SN, which is coupled to the two “pull down” NMOS transistors labeled T33 and T34 in FIG. 1, transitions from an equalized voltage of Vdd/2 to a low voltage of approximately Vss. Now, one of the two NMOS transistors T33 and T34 has a different voltage at its gate input than the other one, and the NMOS transistor with the more positive gate voltage will conduct current, coupling the opposite bit line to a low voltage. In this manner the small differential input voltage from the selected memory cell MC is “sensed” by the sense amplifier SA. In FIG. 2, the unselected bit line ZBL begins falling at this part of the cycle. Because the voltage at the gate of transistor T33 is slightly higher than the initial voltage on bit line ZBL, transistor T33 turns on and begins conducting, and as the voltage on bit line ZBL falls, transistor T33 remains on and conducting. In contrast, transistor T34 has a voltage on its source terminal of bit line BL, plus a delta voltage which is higher than the gate voltage received from bit line ZBL at the beginning of the sense cycle, and thus remains turned off. As the voltage on bit line ZBL falls further in response to the operation of transistor T33, the transistor T34 remains in cut-off state and never conducts, thus the voltage on bit line BL remains at the slightly increased voltage, adding a ΔVBL voltage over the initial voltage Vdd/2 that was present on the bit line BL at the beginning of the sense operation.
Next, as seen in FIG. 2, the prior art memory sensing operation transitions to the “restore” portion of the cycle. In the restore portion of the cycle, (which in prior art sense amplifiers often follows the sense portion by a time period typically of one or more logic gate delays), the control signal SP transitions from the initial, equalized value, to a high potential, for example, Vdd. At this point the P-channel MOS transistors T36 and T37 become important in the sense amplifier SA. In FIG. 1, it can be seen that the node coupled to control signal SP rises to a high voltage. Transistor T36 now has the low voltage on bit line ZBL at its gate, and because it is a PMOS transistor, it turns on and couples the bit line BL to a high voltage from control signal SP. This causes the bit line BL potential to increase from the voltage Vdd/2 (initial voltage on bit line BL) plus the sensed differential voltage ΔVBL to a logical “1” high voltage, or approximately Vdd. The transistor T37 has the voltage on bit line BL on its gate terminal, and because the voltage is higher than at its source terminal, this transistor remains in cut-off. As the voltage on bit line BL increases, transistor T33 turns on further and couples the bit line ZBL to the low voltage on control line SN more completely, thus the two bit lines BL and ZBL are now at a logical “1” and a logical “0,” that is at full logic voltage levels. At this point in the memory cycle, the word line WL is still active so that the high voltage on bit line BL is also coupled into the memory cell MC, that is, the access transistor Tc of memory cell MC will couple this high voltage to the memory cell storage capacitor Cc and thus restore the stored charge for future accesses to this memory cell MC.
Finally, the sense cycle is completed when local bit lines BL and ZBL are coupled to the global bit lines GBL and ZGBL in FIG. 1, by the operation of column select line CSL (see FIG. 2). This action causes the data represented by the voltage potentials on bit lines BL and ZBL to be coupled to the global bit lines, GBL and ZGBL, for use by circuits external to the memory (not shown in FIG. 1).
The sense amplifier, column select and precharge circuits described above present only one known approach to the precharge, sensing and charge sharing operations. Alternatives known in the prior art DRAM devices include using dummy cells to provide reference voltages for sensing. In the dummy cell approach, a voltage may be placed on the non-selected bit line during sensing by selecting a dummy memory cell that is coupled to the bit line, which then eliminates the need for the sensed memory cell to store both a “0” and a “1” charge. Instead, the dummy cell can be operated so that for one logical value, the memory has no voltage effect on the selected bit line, while the dummy cell provides a delta voltage on the non-selected bit line. The sense amplifier then senses the “negative” delta voltage on the bit line (relative to, for example, an increase on the non-selected bit line caused by the dummy cell). U.S. Pat. No. 6,954,371 to Hokari, et al., issued Oct. 11, 2005, describes sensing using dummy cells in various embodiments.
If dummy memory cells are used, extra silicon area is required for the dummy cell capacitors and select transistors, and for the dummy word lines used to select the dummy cells. These area requirements negatively affect the packing density (by increasing the silicon area used per memory storage bit) and are thus undesirable in applications where silicon area is a critical factor, such as in embedded DRAM applications.
Alternative prior art approaches use voltage regulation schemes to create the required voltages for the bit line precharge, sensing and cell plate voltages (positive or negative voltage coupled to one plate of the storage capacitors in the memory cells). U.S. Pat. No. 6,351,426 to Ohsawa, issued Feb. 26, 2002, describes a lowered voltage supply for generating the power supply to the row and column decoders, and for generating the voltage VBL for precharging and for the voltage VPL for the cell plate. Other voltage regulators are described in the prior art. A paper entitled “On-Chip Voltage Regulator with Improved Transient Response,” IEEE Proceedings of the 18th International Conference on VLSI Design, Jan. 3-7, 2005, pp. 522-527, describes an on-chip voltage regulator with a dynamic leakage element at the driver stage of the regulator to improve the transient behavior of the voltage regulator when the load current varies. A paper entitled “Performance Evaluation of CMOS Low Drop-Out Voltage Regulators,” 47th IEEE International Midwest Symposium on Circuits and Systems, Jul. 25-28, 2004, pp. I-141-I-144, Vol. 1, describes three low drop out (LDO) voltage regulators for load regulation and compares the performances of the different circuits.
It is increasingly desirable to embed memory arrays into integrated circuits that also include additional digital or analog circuitry. Lay out features of these embedded memory or e-DRAM arrays must be compatible with other digital circuitry and provide good packing density or memory cells/silicon area. The memory must be very reliable with no cell disturb problems. To reduce power consumption, the trend is to decrease the supply voltage Vdd levels. As is known in the art, the need for reliable operation of DRAM cells in advanced semiconductor processes may limit the minimum power supply Vdd that can be used. Cell disturb problems are also known in the prior art, as feature sizes are reduced in smaller and smaller technologies. The use of an “early write” cycle to increase the amount of time the data is available on the selected bit line during a write operation is desirable. However, it is also known that this approach can lead to cell disturb errors. In cell disturb errors, cells on non-selected bit lines can have their stored charge altered, creating an erroneous memory read operation in future cycles. Prior art circuits require extra write select lines to isolate the non-selected memory cells to avoid the cell disturb problems. These added control lines also increase the silicon area required.
Thus, there is a continuing need for a memory sense amplifier and reference voltage circuit that provides reliable high speed sensing operations, particularly for embedded DRAM arrays, without the need for added write select signals or dummy cells required by the prior art approaches and without the corresponding increases in silicon area.